ASIC Design Verification Engineer
San Jose, CA (onsite/hybrid)
Full-time + Benefits
US Citizen or US Permanent Resident

Responsibilities:
• Test bench development using SystemVerilog and UVM
• Test plan and test case development 
• Experience in developing SV Functional coverage models and SVA assertions and cover properties
• Regression setup and debug RTL level and gate level simulations working with design team

Requirements:
• 5+ years of Design Verification experience with multiple successful tape outs
• Deep knowledge about System Verilog, UVM and verification coverage matrix
• Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)
• Familiar with Synopsys PCIe/CXL Verification IPs
• Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
• Proficient in Perl/Python scripting

#SystemVerilog #UVM #DesignVerification #PCIe #CXL #SoCs
 

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Javier Leon
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)