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Senior PLL Design Engineer
San Diego, CASenior IC Design Engineer
San Diego, CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
Full-Time + Health Benefits + 401K Plan + PTO + Founder Shares
Looking for an IC Designer with experience in PLLs (RF and Clocking), high-speed data converters (ADCs, DACs) and RFCMOS front-end design.
Responsibilities:
• Design of complex building blocks of LC PLL and RO PLL including architecture development and transistor level circuit design
• Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
Required Experience:
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
• Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
• Proficiency in scripting languages like Perl, Python, MATLAB etc. is a plus.
• Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a self-starter, and able to independently drive tasks to completion
• BSEE required, MSEE or PhDEE preferred
#PLL
San Diego, CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
Full-Time + Health Benefits + 401K Plan + PTO + Founder Shares
Looking for an IC Designer with experience in PLLs (RF and Clocking), high-speed data converters (ADCs, DACs) and RFCMOS front-end design.
Responsibilities:
• Design of complex building blocks of LC PLL and RO PLL including architecture development and transistor level circuit design
• Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
Required Experience:
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
• Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
• Proficiency in scripting languages like Perl, Python, MATLAB etc. is a plus.
• Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a self-starter, and able to independently drive tasks to completion
• BSEE required, MSEE or PhDEE preferred
#PLL
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Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)