Senior Design Verification Engineer
Dallas, Texas (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions

Job Description:
• 7+ years of experience in Design Verification
• Strong experience in System Verilog, UVM
• Experience with complex RAL configurations
• Experience with full verification flow including coverage closure
• Experience in high-speed protocols like Ethernet / USB / PCIe / InfiniBand

#DesignVerification #SystemVerilog #UVM #Ethernet #USB #PCIe #InfiniBand
 

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Javier Leon
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)