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ASIC Physical Design Lead (remote)
Dallas, TXASIC Physical Design Lead
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options
Seeking a highly experienced ASIC Physical Design Lead to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 10+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally. In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.
Required Experience:
• 10+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape-outs at advanced technology nodes (16nm to 3nm preferred).
• Deep expertise in Floorplanning, Place & Route, CTS, STA/Timing Closure, Physical verification & sign-off, Power integrity (IR drop/EM), Low power design and UPF
• Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
• Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.
• Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
• Education: BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
#PhysicalDesign #PhysicalImplementation
PHYSICAL DESIGN GROUP on LinkedIn: https://www.linkedin.com/groups/3626111/
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options
Seeking a highly experienced ASIC Physical Design Lead to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 10+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally. In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.
Required Experience:
• 10+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape-outs at advanced technology nodes (16nm to 3nm preferred).
• Deep expertise in Floorplanning, Place & Route, CTS, STA/Timing Closure, Physical verification & sign-off, Power integrity (IR drop/EM), Low power design and UPF
• Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
• Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.
• Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
• Education: BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
#PhysicalDesign #PhysicalImplementation
PHYSICAL DESIGN GROUP on LinkedIn: https://www.linkedin.com/groups/3626111/
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Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)