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Javier Leon
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Senior DFT Engineer - Mentor Tessent Expert
Austin, TXSenior DFT Engineer - Mentor Tessent Expert
Austin, TX (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions
Job Description:
Seeking an experienced Design for Test (DFT) Engineer with a minimum of 8 years in the semiconductor industry, particularly in DFT methodologies and design practices. The ideal candidate will be proficient in Mentor Tessent tools and demonstrate a strong understanding of both Block and SoC-level DFT activities. This role demands expertise in DFT techniques such as Scan, MBIST, and ATPG insertion, as well as advanced debug and pattern coverage improvement skills.
Key Responsibilities:
• Execute DFT strategies and methodologies with a focus on Mentor Tessent flow.
• Perform Scan, MBIST, and ATPG insertion for various design requirements.
• Implement IJTAG and pattern retargeting solutions.
• Insert OCC, EDT, and BSCAN elements for enhanced test coverage and reliability.
• Conduct timing and non-timing simulations to verify DFT integrity.
• Troubleshoot and debug DFT issues with strong analytical skills to enhance test pattern coverage.
• Develop and bring up SDC constraints in DFT mode to ensure accurate timing in test environments.
Requirements:
• Experience: 8+ years in DFT with a solid foundation in semiconductor testing and debug processes.
• Tools Proficiency: Strong hands-on experience with Mentor Tessent flow.
• Technical Skills: Proven expertise in Block and SoC-level DFT activities, including:
- Scan, MBIST, ATPG insertion
- IJTAG implementation and pattern retargeting
- OCC, EDT, BSCAN insertion
• Debugging: Strong debugging skills with the ability to identify and resolve issues, enhance coverage, and optimize patterns.
• Simulation: Skilled in conducting both timing and non-timing simulations for test validation.
• SDC Handling: Familiarity with SDC bring-up in DFT mode for design verification and timing integrity.
#DFTEngineer #Mentor #Tessent #MentorTessent
Austin, TX (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions
Job Description:
Seeking an experienced Design for Test (DFT) Engineer with a minimum of 8 years in the semiconductor industry, particularly in DFT methodologies and design practices. The ideal candidate will be proficient in Mentor Tessent tools and demonstrate a strong understanding of both Block and SoC-level DFT activities. This role demands expertise in DFT techniques such as Scan, MBIST, and ATPG insertion, as well as advanced debug and pattern coverage improvement skills.
Key Responsibilities:
• Execute DFT strategies and methodologies with a focus on Mentor Tessent flow.
• Perform Scan, MBIST, and ATPG insertion for various design requirements.
• Implement IJTAG and pattern retargeting solutions.
• Insert OCC, EDT, and BSCAN elements for enhanced test coverage and reliability.
• Conduct timing and non-timing simulations to verify DFT integrity.
• Troubleshoot and debug DFT issues with strong analytical skills to enhance test pattern coverage.
• Develop and bring up SDC constraints in DFT mode to ensure accurate timing in test environments.
Requirements:
• Experience: 8+ years in DFT with a solid foundation in semiconductor testing and debug processes.
• Tools Proficiency: Strong hands-on experience with Mentor Tessent flow.
• Technical Skills: Proven expertise in Block and SoC-level DFT activities, including:
- Scan, MBIST, ATPG insertion
- IJTAG implementation and pattern retargeting
- OCC, EDT, BSCAN insertion
• Debugging: Strong debugging skills with the ability to identify and resolve issues, enhance coverage, and optimize patterns.
• Simulation: Skilled in conducting both timing and non-timing simulations for test validation.
• SDC Handling: Familiarity with SDC bring-up in DFT mode for design verification and timing integrity.
#DFTEngineer #Mentor #Tessent #MentorTessent
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Javier Leon
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)