Chip-Level Design Verification Engineer
5 openings, immediate start
12+ months assignment with possible extensions
San Jose, San Diego or Irvine (onsite only)
$80 - $100/hr 1099 or Corp-to-Corp
US Citizen or US Permanent Resident

Seeking an experienced Senior Design Verification Engineer with expertise in Chip Level Verification, HDMI, and SystemVerilog/UVM. The ideal candidate will lead verification efforts for complex digital circuits.

Requirements:
• 5+ years of experience in design verification engineering
• Chip-level verification expertise
• Strong System Verilog and UVM skills
• Experience with HDMI and PCIe (Gen5/Gen6) interfaces
• Strong debugging and problem-solving skills
• Excellent communication and teamwork skills
• Prefer Chip Level but if they have good IP experience like AXI, AMBA, I2C, UART, etc are fine as well

#ChipLevel #DesignVerification #ChipLevelVerification #UVM #SystemVerilog

---
Javier Leon
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)